Generally, an IC device may include various square contacts that are connected to one or more transistors. Additionally, the IC device may include a plurality of metal layers that may be utilized to connect the contacts to various signal sources or targets. In some instances, vias may be utilized to connect an upper metal layer to one or more of the contacts. For example, a via may be utilized to connect a segment of a metal-one (M1) layer to a gate contact on a transistor. However, in some instances, a via may not be substantially aligned with the small square surface area of a target contact, which may cause unreliable connection (e.g., a small contact area) between the via and the target contact. Hence, an unreliable connection between the target contact and the segment of the upper M1 layer results, which may cause the device to be unable to function properly or pass certain IC manufacturing quality/reliability tests, which in turn could negatively impact the manufacturing yield of the IC devices. Additionally, layout of certain metal layers in the IC device may impact advancements in node scaling technologies of the IC devices.
FIGS. 1A and 1B are cross-sectional and three-dimensional diagrams, respectively, of an example IC device. Adverting to FIG. 1A, a cross-section of a conventional static random access memory (SRAM) device is illustrated, which includes a silicon substrate 101 and a shallow trench insulating layer 103. Additionally, on the upper surface of the silicon substrate 101 are a plurality of gate electrodes (PC) 105 and a plurality of trench silicides (TS) 107, wherein gate contacts (CB) 109 connect to upper surfaces of PCs 105, and source/drain contacts (CA) 111 connect to upper surfaces of TS's 107. Further, vias 113 connect one or more segments of an M1 layer 115 to upper surfaces of CB contacts 109 and/or CA contacts 111. However, the bottom surface of a via, for example via 113a, may not be completely aligned with an upper surface of a CB contact, e.g. contact 109a (or other CA or CB contacts), which may result in an insufficient contact area for reliable functionality and a proper transfer of power or signals between the two elements.
FIG. 1B illustrates a 3D diagram of the IC device in FIG. 1A where the via 113a is horizontally misaligned with the CB contact 109a. The misalignment between via 113a and CB contact 109a is merely exemplary; many more instances of misalignment may exist in an IC device between vias and both CB contacts and CA contacts. As noted, among considerations in designing and fabricating IC devices are steps for providing sufficient and efficient contact layout designs for providing reliable and economical manufacturing yields of the IC devices.
A need therefore exists for a methodology enabling improved connections between contacts and vias in an IC device and the resulting device.